In recent years, with miniaturization of a device in consequence of an increase in an integration level of a semiconductor circuit, there have risen quality requirements for a silicon single crystal serving as a substrate of the semiconductor circuit and grown by a Czochralski method (hereinafter referred to, for brevity, as the “CZ method”). In particular, there exist defects due to single crystal growth called grown-in defects such as FPD, LSTD, and COP, which deteriorate an oxide film dielectric breakdown characteristic and the characteristics of a device. A decrease in the density and sizes of the defects is regarded as important.
In explanation of these defects, first there will be described below generally known matters for factors to determine a taken in concentration each of a void type point defect called vacancy (hereinafter may be also briefly referred to as V), and an interstitial silicon point defect called interstitial-Si (hereinafter may be also briefly referred to as I) both taken in a silicon single crystal.
In a silicon single crystal, a V region is a vacancy, i.e., a region rich in recessed portions, holes and the like formed due to shortage of silicon atoms, and an I region is a region rich in dislocations and blocks of silicon atoms generated by the presence of excessive silicon atoms. As a result, a neutral (hereinafter may be also briefly referred to as N) region in which atoms are not short or excessive (or rarely short or excessive) is present between the V region and the I region. It has been come out that grown-in defects (FPD, LSTD, COP, and the like) absolutely generate when the V or I is oversaturated, and when the V or I is not saturated, even though the distribution of atoms may be slightly biased, the above defects are not present.
The densities of both the point defects are determined depending on the relationship between a pulling rate (growth rate) of a crystal in the CZ method and a temperature gradient G in the neighborhood of a solid-liquid interface in the crystal. It is confirmed that in the neighborhood of the boundary between the V region and the I region, defects called an OSF (Oxidation Induced Stacking Fault) are distributed in the form of a ring (hereinafter may be also referred to as an OSF ring) when seeing them as a cross section in a direction perpendicular to the crystal grow axis.
These defects due to crystal growth are exhibited as a defect distribution map as shown in FIG. 9 when there is changed from high to low a growth rate of a crystal along a crystal axis by a CZ pulling machine using an in-furnace structure (hot zone: may be also referred to as an HZ) having a temperature gradient in the neighborhood of a usual solid-liquid interface in the crystal.
These defects caused by crystal growth are classified as follows. When the growth rate is relatively high, e.g., about 0.6 mm/min or more, there exist grown-in defects such as FPD, LSTD, and COP due to voids where void-type point defects collect together at a high density in an entire area in a direction of crystal diameter. The region in which these defects exist is called a V region (line (A) in FIG. 9).
When the growth rate is below 0.6 mm/min, with a decrease in growth rate, an OSF ring generates in the periphery of the crystal, and defects of L/D (Large Dislocation: an abbreviation of an interstitial dislocation loop, LSEPD, LFPD or others) which are considered to be due to a dislocation loop exist outside the ring at a low density. The region where these defects exist is called an I region (may be also referred to as an L/D region). In addition, when the growth rate is lowered to about 0.4 mm/min or less, the OSF ring aggregates and becomes extinct about the center of the wafer, thereby the entire region turning into the I region (line (C) in FIG. 9).
In recent years, the presence of a region, called an N region, which does not include FPD, LSTD, and COP due to the voids, and LSEPD and LFPD due to the dislocation loop is detected outside the OSF ring between the V region and the I region. It is reported that the N region exists outside the OSF ring, and when the N region is subjected to an oxygen precipitation heat treatment and then the contrast of the precipitation is checked by X-ray observation or the like, oxygen is rarely precipitated therein and the N region is on the I region side which is not so rich that LSEPD and LFPD are formed.
Since the N region exists diagonally to the growth axis direction in a usual method when a growth rate is decreased, the N region exists partly on a wafer surface (line (B) in FIG. 9). As to the N region, the Voronkov theory (V. V. Voronkov; Journal of Crystal Growth, 59 (1982) 625 to 643) advocates that a parameter, i.e., F/G that is a ratio of a pulling rate (F) to a temperature gradient (G) in an axial direction of a crystal solid-liquid interface determines a total concentration of point defects. Depending on the theory, since the pulling rate should be constant on the wafer surface, due to a distribution of the temperature gradient (G) on the wafer surface, for example, there could be only obtained a crystal in which the N region is sandwiched between the V region at the center and the I region at the periphery.
Recently, by improving the distribution of the temperature gradient (G) on the wafer surface, for example, when the crystal is pulled while gradually decreasing the pulling rate (F), there can be produced a crystal where the N region which exists only diagonally in a prior art spreads on a lateral entire surface at a certain pulling rate. In order to longitudinally enlarge the crystal where the N region spreads on a lateral entire surface, it is enough to some extent to pull the crystal while keeping a pulling rate at which the N region laterally spreads. In addition, considering the fact that the temperature gradient (G) changes in company with the growth of crystal, the change of the temperature gradient (G) is compensated, and the pulling rate is controlled such that the F/G is constant; therefore the crystal portion where the N region entirely spreads can also be enlarged in the growing direction (for example, JP A 8-330316).
The N region is further classified into an Nv region (a region rich in the voids) adjacent to the outside of the OSF ring and an Ni region (a region rich in the interstitial silicon) adjacent to the I region. It became clear that when performing thermal oxidation treatment, in the Nv region, there is generated a large amount of oxide precipitates and in the Ni region, there are rarely generated oxide precipitates (for example, JP A 2001-139396).
However, it has become clear that a very large number of oxide film defects may be generated even in a single crystal where an N region spreads on the entire surface, an OSF ring is not generated when performing thermal oxidation treatment, and FPD and L/D are not present on the entire surface. This is a cause of deteriorating electric characteristics such as an oxide film dielectric breakdown characteristic. In order to realize excellent electric characteristics, there is not satisfied the conventional single crystal where the N region spreads on the entire surface, and further improvements are desired.
Some of the present inventors have more exactly examined an N region by a Cu deposition method and have found that there exists a region Dn in which defects detected by the Cu deposition method drastically are generated, and which exists in the N region outside the OSF region and in a part of an Nv region where oxide precipitates easily generate after performing precipitation heat treatment (FIG. 10). The inventors have located the fact that the Dn region is a cause of deteriorating electric characteristics such as an oxide film dielectric breakdown characteristic, which already has been taught (JP A 2002-201093).
Therefore, if there can be spread on the entire wafer surface a region which is the N region outside the OSF region and is free from a defect region Dn detected by the Cu deposition method, there can be obtained a wafer which is free from the various grown-in defects and can reliably improve an oxide film dielectric breakdown characteristic or the like.
The Cu deposition method is a wafer evaluation method that can accurately measure the positions of defects of a semiconductor wafer, can improve detection limit to the defects of the semiconductor wafer, and can accurately measure and analyze more microscopic defects.
In a concrete wafer evaluation method, an insulating film having a predetermined thickness is formed on a wafer surface, and the insulating film on a defective portion formed in the vicinity of the surface of the wafer is broken to deposit an electrolyte such as Cu at the defective portion. More specifically, the Cu deposition method is an evaluation method using the fact that when a potential is applied to an oxide film formed on the wafer surface in a liquid in which Cu ions are dissolved, a current flows in a portion where the oxide film is deteriorated, and the Cu ions are deposited as Cu. It is known that defects such as COP are present at a portion where the oxide film is easily deteriorated.
The defective portion of the wafer on which Cu is deposited are analyzed under a focused light or directly visually analyzed to evaluate the distribution and the density thereof. In addition, the defective positions can also be checked with a microscopic observation such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM).
The terms will be explained below.    1) FPD (Flow Pattern Defect): A wafer is sliced from a grown silicon single crystal rod, a surface distorted layer is removed by etching using a liquid mixture of a hydrofluoric acid and a nitric acid, and the surface is etched (Secco etching) by a liquid mixture of K2Cr2O7, a hydrofluoric acid and water to form pits and a ripple pattern (a flow pattern). The flow pattern is called an FPD, and the higher the FPD density on the wafer surface, the more the poor oxide film dielectric breakdown characteristic (see JP A 4-192345).    2) SEPD (Secco Etch Pit Defect): When performing the Secco etching described above in the FPD, a defect which is accompanied by a flow pattern is called an FPD, and a defect which is not accompanied by a flow pattern is called an SEPD. It is conceivable that an SEPD (LSEPD) having 10 μm or more is due to a dislocation cluster; therefore when a device includes a dislocation cluster, current leaks through the dislocation, and the device does not function as a P-N junction.    3) LSTD (Laser Scattering Tomography Defect): A wafer is sliced from a grown silicon single crystal rod, a surface distorted layer is removed by etching using a liquid mixture of a hydrofluoric acid and a nitric acid, and then the wafer is cleaved. Infrared rays are incident on the cleaved surface (or the wafer surface) to detect rays emitted from the wafer surface (or the cleaved surface), so that scattered light caused by defects present in the wafer can be detected. This defect is called a LSTD. A scattering object observed here has been reported at an academic society or the like, and is regarded as an oxide precipitate (see Japanese Journal of Applied Physics Vol. 32, p. 3679, 1993). In addition, a recent study has reported that the scattering object is an octahedral void (hole).    4) COP (Crystal Originated Particle): This defect causes deterioration of the oxide film dielectric breakdown characteristic of the central portion of a wafer. The defect which is an FPD in the Secco etching is a COP in the SC-1 cleaning (cleaning by a liquid mixture of NH4OH: H2O2: H2O=1:1:10) because the liquid mixture serves as a selective etchant. The diameter of the pit is 1 μm or less, and is checked by a light scattering method.    5) L/D (large Dislocation: an abbreviation of an interstitial dislocation loop): This defect includes an LSEPD, an LFPD, and the like, and is a defect which is considered to be due to a dislocation loop. An LSEPD is an SEPD having 10 μm or more as described above. An LFPD is an FPD having a distal-end pit having a size of 10 μm or more, and is also considered to be due to a dislocation loop.
On the other hand, a silicon single crystal grown by the Czochralski method includes interstitial oxygen at a concentration of 1018 atoms/cm3 as an impurity. The interstitial oxygen is precipitated by a supersaturation in a thermal history from solidification to cooling to a room temperature in the crystal growth step (hereinafter may be briefly referred to as a crystal thermal history) or in the heat treatment in the fabricating step for a semiconductor device, so that a precipitate of a silicon oxide (hereinafter may be also referred to as an oxide precipitate or simply a precipitate) is formed.
The oxide precipitate effectively serves as a site that captures a heavy metal impurity contaminated in device fabrication processes (Internal Getting: IG) to improve device characteristics or a yield. For this reason, as one of qualities of a silicon wafer, the IG capability is regarded as important.
The process of oxygen precipitation includes the formation of precipitation nuclei and the growth process thereof. In a usual as-grow wafer, the nucleus formation progresses in the crystal thermal history, and the nuclei are largely grown by heat treatment in the device fabrication processes and other processes performed thereafter, the grown nuclei being detectable as oxide precipitates. Therefore, the oxide precipitates which are present before loading the wafer into the device fabrication processes are extremely small, and do not have the IG capability. However, by loading the wafer into the device fabrication processes, the oxide precipitates are grown to large ones to have the IG capability.
On the other hand, in recent device fabrication processes, with an increase in diameter of a wafer to be used, there progresses lowering in temperature and shortening in processing time. For example, a series of device fabrication processes are performed at a temperature of 1000° C. or less, or RTP (Rapid Thermal Processing) that requires only a heat treatment time of about several ten seconds has been frequently used. Since all the heat treatment performed in the device fabrication processes may totally correspond to only the heat treatment performed at 1000° C. for about 2 hours, unlike the prior art, growth of oxide precipitates in the device fabrication processes cannot be expected. For this reason, in the device fabrication processes where low temperature and short processing time are realized, it is necessary for the wafer to have the excellent IG capability before loading it into the device fabrication processes. More specifically, large oxide precipitates detectable before loading the wafer into the device fabrication processes are desirably formed at a high density.
On the other hand, the presence of oxide precipitates in a device fabricating region in the vicinity of the wafer surface deteriorates device characteristics. For this reason, it is desirable that oxide precipitates are not present in the vicinity of the wafer surface.
In a general CZ wafer, as so-called grown-in defects generated by a thermal history when pulling crystal, in addition to grown-in oxygen precipitation nuclei, there exist voids defects formed by aggregation of vacancies. When the voids are exposed on the surface of a mirror-polished wafer, the voids turn into surface pits called COP. The presence of COP and voids in the device fabricating region deteriorates device characteristics. In particular, it is known that the COP and voids deteriorate an oxide film dielectric breakdown characteristic that is an important characteristic. From the above fact, it is desirable that not only the oxide precipitates but also the COP and voids are not present in the device fabricating region (usually at a depth of about several μm from the surface) of the wafer surface layer.
In order to annihilate the COP and voids in the wafer surface layer, high-temperature heat treatment at about 1200° C. may be performed in a hydrogen atmosphere or an inert gas atmosphere such as an argon atmosphere. In this case, it is preferable that the IG capability is given. For this reason, as a method for simultaneously realizing elimination of the COP and voids in the vicinity of the wafer surface and formation of oxide precipitates in the wafer bulk, methods for adding nitrogen when growing a crystal are proposed (for example, JP A 11-322490, 11-322491, and 2000-211995, and the like).
In the wafer added with nitrogen, voids can be easily eliminated by the high-temperature heat treatment in the vicinity of the wafer surface because the voids decrease in size, and since grown-in precipitation nuclei formed by a crystal thermal history increase in size, the precipitation nuclei are grown without being eliminated even in the high-temperature heat treatment in the wafer bulk to form oxide precipitates, with the result that the IG capability is given.
However, even when the wafer having nitrogen added thereto is used, high-temperature heat treatment at about 1200° is required to eliminate the voids in the surface layer; in some cases, small size voids which belong to the size level not detectable may be left. In addition, since large grown-in precipitation nuclei are thermally stable, they are not easily eliminated even in the wafer surface layer and may be left in the surface layer. When these defects are left in the surface layer, there occurs a problem that device characteristics are deteriorated.
In addition, when nitrogen is added when growing a crystal, the crystal producing steps are complicated, and control of a nitrogen concentration requires much labor.